144 lines
4.5 KiB
Markdown
144 lines
4.5 KiB
Markdown
# GCC Intro
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The GNU C and C++ compiler are called gcc and g++, respectively.
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The GNU Toolchain, including GCC, is included in all Unixes. It is the standard compiler for most Unix-like operating systems. Test its installed with
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```bash
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gcc --version
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```
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## Hello World - C
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The first program is a simple "Hello World" in C. To compile the hello.c:
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```bash
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gcc hello.c
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```
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This compiles and links source file hello.c into executable a. The default output executable is called 'a.out'. To run the program:
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```bash
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# grant executable rights
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chmod a+x a.out
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# run
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./a.out
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```
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To specify the output filename, use -o option:
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```bash
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gcc -o hello hello.c
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chmod a+x hello
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./hello
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```
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## Hello World - C++
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You need to use g++ to compile C++ program, as follows. We use the -o option to specify the output file name. It's very similar to gcc.
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```bash
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g++ -o hello hello.cpp
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chmod a+x hello
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./hello
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```
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There are a few more GCC Compiler Options. A few commonly-used GCC compiler options are:
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- o: specifies the output executable filename.
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- Wall: prints "all" Warning messages.
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- g: generates additional symbolic debuggging information for use with gdb debugger.
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## Compile multiple source files
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Suppose that your program has two source files: file1.cpp, file2.cpp. You could compile all of them in a single command:
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```bash
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g++ -o myprog.exe file1.cpp file2.cpp
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```
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Usually compile each of the source files separately into object file, and link them together in the later stage. In this case, changes in one file does not require re-compilation of the other files.
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```bash
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g++ -c file1.cpp
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g++ -c file2.cpp
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g++ -o myprog.exe file1.o file2.o
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```
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## GNU Make
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The `make` utility automates the mundane aspects of building executable from source code. `make` uses a so-called makefile, which contains rules on how to build the executables.
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Simply create a file named `makefile` in the same directory as the source file, this file contains rules to build the exectable.
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To run the the `make` utility use
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```bash
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make
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```
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Running make without argument starts the target "all" in the makefile.
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### Rulesets
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A makefile consists of a set of rules. A rule consists of 3 parts: a target, a list of pre-requisites and a command, like
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```bash
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target: pre-req-1 pre-req-2 ...
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command
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```
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You can also specify the target to be made in the make command by using its targets name of the makefile
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```bash
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make clean
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```
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### Comments
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Makefiles can be commented by prevailing a line with `#` like
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```makefile
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# this is a comment
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target: requisites ...
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command
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```
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### Variables
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Next to that you can use Variables for a more programatically way of building your projects. Variables begin with a `$` and are enclosed within parantheses or braces
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```makefile
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$(CC), $(CC_FLAGS), $@, $^.
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```
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Automatic variables are set by make after a rule is matched. There include:
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- `$@`: the target filename.
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- `$*`: the target filename without the file extension.
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- `$<`: the first prerequisite filename.
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- `$^`: the filenames of all the prerequisites, separated by spaces, discard duplicates.
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- `$+`: similar to $^, but includes duplicates.
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- `$?`: the names of all prerequisites that are newer than the target, separated by spaces.
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E.g. an advanced makefile could look like
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```makefile
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all: hello.exe
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# $@ matches the target; $< matches the first dependent
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hello.exe: hello.o
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gcc -o $@ $<
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hello.o: hello.c
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gcc -c $<
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clean:
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rm hello.o hello.exe
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```
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### Virtual Paths
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Use VPATH (uppercase) to specify the directory to search for dependencies and target files, e.g.
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```makefile
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# Search for dependencies and targets from "src" and "include" directories
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# directories are separated by space
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VPATH = src include
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```
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Use vpath (lowercase) to be more precise about the file type and its search directory, e.g.
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```makefile
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# Search for .c files in "src" directory; .h files in "include" directory
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# The pattern matching character '%' matches filename without the extension
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vpath %.c src
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vpath %.h include
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```
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### Pattern Rules
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A pattern rule, which uses pattern matching character `%` as the filename, can be applied to create a target, if there is no explicit rule. For example,
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```makefile
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# Applicable for create .o object file.
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# '%' matches filename.
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# $< is the first pre-requisite
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# $(COMPILE.c) consists of compiler name and compiler options
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# $(OUTPUT_OPTIONS) could be -o $@
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%.o: %.c
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$(COMPILE.c) $(OUTPUT_OPTION) $<
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# Applicable for create executable (without extension) from object .o object file
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# $^ matches all the pre-requisites (no duplicates)
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%: %.o
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$(LINK.o) $^ $(LOADLIBES) $(LDLIBS) -o $@
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```
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Find more informations at [GNU GCC](http://gcc.gnu.org/) |